{"product_id":"9783540423294","title":"Power-Aware Computer Systems : First International Workshop, Pacs 2000, Cambridge, Ma, Usa, November 12, 2000, Revised Papers (Lecture Notes in Comput","description":"\u003cp\u003eThe phenomenal increases in computer system performance in recent years have been accompanied by a commensurate increase in power and energy dissipation. The latter has directly resulted in demand for expensive packaging and cooling technology, an increase in product cost, and a decrease in product reliability in all segments of the computing market. Moreover, the higher power\/energy dissipation has signi cantly reduced battery life in portable systems. While - stem designers have traditionally relied on circuit-level techniques to reduce - wer\/energy, there is a growing need to address power\/energy dissipation at all levels of the computer system. We are pleased to welcome you to the proceedings of the Power-Aware C- puter Systems (PACS 2000) workshop. PACS 2000 was the rst workshop in its series and its aim was to bring together experts from academia and industry to address power-\/energy-awareness at all levels of computer systems. In these p- ceedings, we bring you several excellent research contributions spanning a wide spectrum of areas in power-aware systems, from application all the way to c- pilers and microarchitecture, and to power\/performance estimating models and tools. We have grouped the contributions into the following speci c categories: (1) power-aware microarchitectural\/circuit techniques, (2) application\/compiler power optimizations, (3) exploiting opportunity for power optimization in - struction scheduling and cache memories, and (4) power\/performance models and tools. Power-Aware Microarchitectural\/Circuit Techniques.- System-Level Design Methods for Low-Energy Architectures Containing Variable Voltage Processors.- Ramp Up\/Down Functional Unit to Reduce Step Power.- An Adaptive Issue Queue for Reduced Power at High Performance.- Application\/Compiler Optimizations.- Dynamic Memory Oriented Transformations in the MPEG4 IM1-Player on a Low Power Platform.- Exploiting Content Variation and Perception in Power-Aware 3D Graphics Rendering.- Compiler-Directed Dynamic Frequency and Voltage Scheduling.- Exploiting IPC\/Memory Slack.- Cache-Line Decay: A Mechanism to Reduce Cache Leakage Power.- Dynamically Reconfiguring Processor Resources to Reduce Power Consumption in High-Performance Processors.- Power\/Performance Models and Tools.- TEM2P2EST: A Thermal Enabled Multi-model Power\/Performance ESTimator.- Power-Performance Modeling and Tradeoff Analysis for a High End Microprocessor.- A Comparison of Two Architectural Power Models.\u003c\/p\u003e","brand":"Springer Verlag","offers":[{"title":"Default Title","offer_id":42564008673355,"sku":"00000_00000_00000_00000","price":1960.57,"currency_code":"THB","in_stock":true}],"url":"https:\/\/kinokuniya.co.th\/products\/9783540423294","provider":"Books Kinokuniya Thailand","version":"1.0","type":"link"}